computer architecture – A 32 – bit wide main memory unit with a capacity of 1 GB is built using 256M X 4-bit DRAM chips


A 32 – bit wide main memory unit with a capacity of 1 GB is built using 256M X 4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 2^14. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closet integer) of the time available for performing the memory read/write operations in the main memory unit is _______ .

I calculated that the no of DRAM chips needed is 32. Now each DRAM have rows = 2^14
and columns 2^16 also as we can refresh the rows in parallel and since for one memory cell the time is 50 nanoseconds so for 2^16 columns we will need 2^16 * 50 nano sec ?…Is my approach right