# computer architecture – How to compute the Cycles in a pipelined single cycle processor

I’m an undergrad studying computer engineering and I’m in my first of many courses on computer organization/architecture. In the lectures and online I see diagrams like the one pictured below from the university of washington. In general, it seems that the number of cycles in a single cycle pipelined architecture can be derived by the equation

$$C = text{stages} + text{Instruction Count} – 1\\$$

That seems to fit with the diagram, each instruction must pass through the same 5 stages. The first instruction has no idle resources and so must use clock cycles equivilent the number of stages. Each other instruction may take advantage of the idle resources and so must only add a single cycle each to process.

My first question is whether my understanding is correct. My second question is what would happen if one of these instructions encountered a data hazard and was forced to stall? How would that affect the number of cycles required? I assume it would go up 1 cycle per stall, but I don’t know for certain.