digital circuits – What is the behavior of the given counter?

I found the following question –

For the circuit shown in the figure, the delay of the bubble NAND gate is 2ns and that of the counter is assumed to be zero.

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If the clock frequency (Clk) is 1 GHz, the counter behaves like a

(A) mod-5 counter
(B) counter mod-6
(C) counter mod-7
(D) mod-8 counter

What I can see is that, in this particular case, the clock period is less than the delay in the NAND gate. But I am unable to see how that will affect the counter exactly!